Design of a CPL-Based Pipeline Multiplier Accumulator for 32-Bit CPU
Yang Xingzi · 2004
To meet the specification of a CPU, a 5-stage pipeline structure is usually adopted for a synthesized multiplier accumulator, which, however, leads mismatch between MAC pipeline and instruction's pipeline, making the control logic more complex. A high-speed CPL-based multiplier accumulator circuit is presented in the paper. The circuit reduces the number of MAC pipeline stages from 5 to 3, which matches the instruction's pipeline, simplifying the control logic and cutting down both the power and chip area.