The Dual-loop Synthesizer for W-CDMA MT
Xiao‐Wei Zhu · 2003
This paper focuses on the special PLL module for W-CDMA Mobile Terminal. The contents include: frequency synthesizing method selection, design and simulation of phase-locked loop based on the National semiconductor′s dual-PLL chip LMX2350, design and simulation of voltage-controlled oscillator at 1.9 GHz, and design of voltage-controlled oscillator at 380 MHz. At the end of this paper, the application of this module in W-CDMA mobile terminal system is shown.