The design of eight-bit binary reversible synchronous counter with GAL device
Jun Tian · 2000
The characteristics of the structure and the performance of major devices of the programmable logic device——the generic array logic(GAL) device are introduced. Then the method of using GAL to design the eight bit binary reversible synchronous counter and a kind of logic design software——CUPL language are also introduced.It can be used as a reference for the people who often use PLD to improve their digital system design.