Research of Network on Chip Topology
Changshan Wang · China Integrated Circuit · 2007
With the complexity of designing SoC architecture increasing,traditional bus-based architecture has become the bottleneck of communication among IP blocks. In order to meet the requirements of scalability,energy consumption,size,clock asynchronization,reusability,QoS etc in large-scale integrated circuits,the new design method-network on chip (NoC) came into being,which is a new innovation compared to the original design patterns. In this paper,first,we introduced the technical characteristics in NoC and the key technology in this area; Then we study the common NoC topology in detail and point out the advantages and shortcomings of each one; Finally,By analyzing the performance parameters of each topology,we can get integrated performance comparison.