Gate-level timing simulation of the SoC embedded with MIPS core and power estimation
Liang Jin · Application of Electronic Technique · 2008
Timing verification is the key step in the SoC design flow。In the design of the HDTV SoC chip embedded with the MIPS core, we make the software and hardware co-simulation with the VMC model of MIPS, on the base of SoC gate-level netlist. In the process of verification ,the VMC load the boot loader program, which can verify the function and timing of the SoC chip effectively. In the process of the simulation, a VCD (value change dump) file can be obtained to help to estimate and analysis the power。