Reduction Rules for Petri Net Based Representation for Embedded Systems
Chuanliang Xia · Jisuanji kexue yu tansuo · 2008
The research concentrates on the aspects related to reduction rules for Petri Net based Representation for Embedded Systems (PRES+). The major motivation of this work is to give correctness-preservation transformations to improve the verification efficiency. It proposes a set of reduction rules to reduce PRES+ nets to the equivalent reduced PRES+ nets. Reductions for two system models demonstrate the efficiency of this reduction rules on practical applications.