Verilog Design and Research of Finite State Machine
Yuzhuo Fu · Microelectronics & Computer · 2004
This paper studies different state encoding styles and Verilog descriptions of Finite State Machine (FSM). Based on these styles, benefits and shortages are described. Furthermore, as a FSM design example, a DMA Arbiter is presented and implemented in seven ways discussed in this paper. The timing and area results of Design Compiler synthesis are also analyzed.