Full-custom Implementation of Fast Floating-point Adder
Guanghai Jin · Computer and Modernization · 2004
The full-custom design of a pipelined floating-point adder conforming to IEEE 754 is presented,which is integrated with a 32-bit high-performance CPU of SMIC 1.8V 0.18um 1p6m CMOS process.Based on the research of the fast algorithm and the full-custom back end implementation,this floating-point adder is expected to achieve high performance,low power dissipation,small chip area,and low cost.