Design and Implementation of a Modified High Speed Scalable Dual-Field Modular Multiplier
Yingjian Yan · Microelectronics & Computer · 2009
Based on multi-precision dual-field Montgomery modular multiplication algorithm,a scalable dual-field modular multiplier is implemented.Its processing cell replaces conventional dual-clock architecture with a novel triple-clock architecture that shortens the critical path and boosts the clock frequency.The performance is improved so efficiently that it is only 0.23μs @240MHz to compute a 256bit modular multiplication overGF(p)under the SMIC0.18μm CMOS standard cell technology.