Register transfer level verification system based on hybrid satisfiability engine
Yan Xiao-lang · Journal of Zhejiang University(Engineering Science) · 2010
A new verification method for Verilog described register transfer level (RTL) was proposed to improve verification performance.The method transformed a verification problem to RTL satisfiability (SAT) one based on hybrid SAT engine.The synthesis engine replaced the implementation of arithmetic circuit with abstract description compared with traditional method.Because the abstract level was much higher,the verification engine was not be involved in details of lower-level implementation.Then the system performance was greatly improved.Experimental results show that RTL verification flow based on hybrid SAT engine has obvious advantage and the verification time for complex circuits can even be reduced as much as 99%.