Comparison between system verilog and verilog in modeling Finite State Machine(FSM)
Dongming Xu · Journal of Xi'an University of Post and Telecommunications · 2008
Finite State Machine(FSM) is not only a tool for describing the circuit,but a way for thinking,therefore,it is widely used in the areas of digital circuit design,such as system level modeling and Register Transfer Level(RTL) modeling.So how to code efficient,maintainable and reusable RTL coding,is not only come up with new challenge to the hardware engineer,but to the abstract level,syntax and grammar of hardware description language(HDL).This paper details RTL coding and synthesis techniques of Finite State Machine(FSM) design using the new SystemVerilog capabilities.What is more,efficient existing RTL coding styles are compared to new SystemVerilog enhanced coding styles,so as to show the advantage of SystemVerilog in modeling FSM.