A Pipeline Double Precision Floating-Point Divider with Fixed Latency
Guo Li · Microelectronics & Computer · 2008
In this paper,we propose a fixed latency pipelined divider using modified Taylor-series expansion for floating point operations.The divider has 5 stages pipeline and its ROM only 2.5kB.Synthesize on FPGA,the proposed divider reduces chip area by about 33% than the other pipelined divider.