VHDL implementation of the Q-Coder
Zhang Xiao-san · Information technology newsletter · 2006
A binary arithmetic coder named Q-Coder that is suit for being performed in hardware is introduced,which is also performed using VHDL.The pre-simulation is carried out with Active-HDL and synthesis and the post-simulation are conducted with QuartusⅡ.The estimated clock is 36.3MHz.