Design of Low-power Decimal Counter with Reset Based on CTGAL Circuit
Pengjun Wang · Journal of Ningbo University · 2009
Based on the working principle,counter structure and Clocked Transmission Gate Adiabatic Logic circuits,a design scheme of decimal counter with reset is proposed.The scheme makes use of clocked transmission gate to sample the input signals,then output loads are charged or discharged in a fully adiabatic manner using bootstrapped NMOS and CMOS-latch structure.The scale alterable counter is implemented by adopting the proposed reset structure.PSPICE simulation results substantiate the validity of the functionality of the designed circuits,which can save up to about 82% energy compared to generic CMOS decimal counter at the same frequency.