SRAM cluster of boundary scan interconnect testing at board level
Guixiang Li · Semiconductor Technology · 2004
Due to the expense and complexity of BS circuitry, the widely-use SRAMs on mostmodern telecommunication circuit boards seldom contain BS architecture. In this paper, a methodol-ogy and a architecture for testing SRAM clusters interconnect at board level are presented. Themethodology can test the large numbers of board-level interconnect at the control, data andaddress lines of cluster SRAMs, and the design procedure requires fewer test vestors.