Design and Implemention of CTC Decoder Based on FPGA
Shengbing Zhang · Microelectronics & Computer · 2007
This paper proposes a highly effective CTC decoder Based on Enhanced Max-log-MAP algorithm it has better performance and further reduces the arithmetic complexity.A C language model is set for verifying the process of encoding and decoding.Dividing the decoder by modules,the technique of interleaver and slid window is also used to improve the speed of decoding and reduce the memory of decoder.At last,the whole design is described with Verilog HDL and implemented successfully on the Cyclone II of Altera.