Design and Implementation of Verilog to C Translation Tool
Fuxin Zhang · Jisuanji gongcheng · 2006
A method of generating equivalent C/C++ code from Verilog hardware descriptions is proposed in this paper.Besides,a way of simplifying behavioral model of Verilog and an optimization algorithm on nonblocking assignments are given.There are also some guidelines of memory arrangement.The generated code is then compiled by C/C++ compiler to an executable program which can perform simulation directly.The test results based on Godson RTL code show that the simulation speed is much fast than that of common simulation software and this method does help a lot in performance evaluation and analysis.