Design and implementation of mode reconfigurable NAND flash error correcting system
Chao Jian Xiang · Journal of Central South University(Science and Technology) · 2013
Mode reconfigurable error correcting circuit was presented for NAND flash memory.This circuit can effectively avoid larger error bits than the designed error correcting bits.Hereinafter,a circuit design method of parallel BCH code was brought up,and a kind of BM iterative algorithm hardware implementation was deduced without finite field inverse operation.Based on the multiplexing technology of the codec algorithm circuit and combing pipeline technology with ping-pong operation technology,the performance of the correcting system is improved ingeniously while the increase of the cost is acceptable.The error correcting system circuit is implemented and tested in the FPGA chip of the EP3CE15E22C8 series.Under the same system operating frequency,eight times greater data throughput rate are achieved than those of the traditional serial circuits with only double hardware cost.In comparison with traditional NAND flash error correcting circuit,the present error correcting circuit is relatively independent and portable,and can meet the requirement of several applications.