Design and Implementation of LDPC Decoder with High Throughput
Haige Xiang · Beijing Daxue Xuebao. Zirankexueban · 2007
The decoding algorithm is investigated and an improved architecture for the decoders is presented.The architecture makes variable nodes and check nodes work for two different code words at the same time.And the architecture is not only fit for full-parallel LDPC decoders but also fit for the semi-parallel decoders which are mostly used in the practical communication systems.A semi-parallel LDPC decoder with code length equal to 1008?bits is implemented based on this architecture on FPGA platform.Synthesize results show that the improved architecture can improve the efficiency of the logic cells.And the throughputs of information bits attain 45 Mbps which is twice of the throughputs of the decoder without the improved architecture.