Verification Method Based on Property Checking of SystemC Design
Ruilian Zhao · Modern Electronics Technique · 2009
Today,complex systems are modeled on a high level of abstraction.In this context,C/C++ based description languages,such as SystemC,become very important.A method according to property checking of SystemC design is introduced,and how to describe linear temporal logic property of circuit system is discussed.The basic form of property description is defined and the method of how to use SystemC to describe the property is elaborated.In addition,SystemC language is introduced,and the approaches of property description and property checking during simulation are discussed.The deficiencies of the current property checking are also analyzed.As a result,two improvements for property checking,and the experiment results demonstrate the effectiveness of our methods are proposed.