Formal verification of word-level specifications based on weighted generalized lists
Guanjun Wang · Harbin Gongcheng Daxue Xuebao/Journal of Harbin Engineering University · 2007
Formal verification has become one of the most important steps in circuit design.As a result,verification of high-level hardware description languages(HDL),like VHDL,is becoming increasingly important to ensure effective tools for circuit design.A complete set of datapath operations are presented in this paper that can make a formal verification based on weighted generalized lists(WGLs).The WGL representation of world-level functions and HDL operations are also discussed.The techniques allows a direct transformation of HDL to WGLs.A new algorithm is proposed based on WGLs for modulus operation and division.These operations are the core of an efficient verification procedure proposed in this paper.The verification tool is completely automatic and experimental results verify the efficiency of this approach.