Low power instruction Cache design
Zhang Shudan · Computer Engineering and Applications Journal · 2011
This paper designs a low power instruction Cache by adding a Line Buffer between CPU and instruction Cache to reduce the on-chip cache memory access activities,consequently it decreases the energy consumption of the Cache memory.What’s more,it also minimizes the Cache miss penalty by adding refill engine to the Line Buffer.Simulation results show that the design can not only reduce the power consumption but also improve the instruction Cache performance.