Design and implementation of GPS clock tame circuit based on FPGA
Le Zhang · Electronic Design Engineering · 2014
To meet the requirements of system for higsh precision clock,according to the characteristics of crystal clock without random error and the global positioning system(GPS) clock no accumulated error, this paper proposes a scheme of using GPS second signal to tame crystal oscillator clock to realize high precision clock. The scheme based on the principles of digital PLL frequency multiplier by measuring the phase error of the GPS seconds clock with the local clock to adjust the ratio of the clock divider circuit, real-time eliminating crystal clock cumulative error,So as to realize high precision system clock. Verified by practical, the method in the use of 16.369MHz temperature-compensation crystal oscillator, under the condition of GPS signals effectively the output clock error is less than 0.1ppm, GPS signal failure after 1 hour after the error is less than 0.3ppm.