The IP Core Design of Floating-point Adder
Xue Zhong-ji · Microcomputer Information · 2008
FPA (floating point adder) is one of the most useful operations in floating calculation. In this paper, we apply the structure of adder with five level pipeline, and encode it by using Verilog HDL. After synthesizing and simulating with 0.18um CMOS library provided by SMIC , the working frequency of the adder achieves 500MHz.