Efficient Sorting Architecture for Radix-4 FFT in FPGA
Xian Chu-hua · Nanjing Hangkong Hangtian Daxue xuebao · 2005
The novel sorting architecture of the FFT processor is presented based on radix-4 decimation-in-time algorithm. By combining both the pipeline and parallel schemes, the proposed radix-4 butterfly uses three real multipliers and nine real adders, which leads to reduce multipliers of conventional 75%. The processor based on FPGA can operate at 100 MHz and calculate the 1 024 floating-point complex FFT in 51 29 μs. So it satisfies the needs of both small area and high speed. Furthermore, since the sorting architecture can be easily upgraded for radix-8, radix-16FFT algorithm, and donot increase the clocks required for computing a radix-r butterfly, it will be more efficient for the high radix.