Design Of Floating-Point Multiplier Used In The Embedded Processors
Pan Yong-feng · Microelectronics & Computer · 2008
This paper presents a cascade floating-point multiplier with compressors by employing the idea of compressing products of multiply and modifying the traditional cascade multiplier. Analyses of several multipliers with different compression architectures are given. The results of experiment shows that the multiplier can improve the performance of the traditional cascade multiplier efficiently, and has less area compared with the array multiplier.