The Circuit Design For Matrix high-speed Calculation
Shen Xiaolin · Microcomputer Information · 2009
This design is targeted at a small size,operational speed and high performance requirements of the special occasions design of the 32-bit floating-point matrix multiplication modules,using VHDL hardware description language, and FPGA implementation. Logic design algorithm used adder structure, called the multiplication modules, using Adder to achieve summation. The first stage, the principle is to the small band of big bands. Then the final summation and the results were standardized. There are two non-standardized; Finally rounding, according to a 0 into homes,using IEEE-754 provided for the rounding to the nearest model for the final right to deal with the homes and reach adder. The paper gives a 32-bit floating-point matrix multiplication in the Quartus II on the simulation results of operations, and the error analysis.