Efficient Area Reduction Solution for Hardware Implementation of AES Algorithm
Jianguo Liu · Jisuanji gongcheng · 2006
This paper proposes a novel efficient area reduction solution for hardware implementation of the advanced encryption standard(AES) algorithm which works in SSX11-140 secure processor architecture.It presents an optimization design in subkeys saving and MixColumns/InvMixColumns operations;The key expansion and the encryption/decryption implementations share the key components such as S-BOX and mix columns.The experiment result shows that the design can satisfy the requirements of the factual application,in the same time it can reduce the area cost effectively,and can be applied in smart architectures.