Design and optimize of the TLB in Cache
Qing Ling · Journal of Suzhou University · 2005
In nowadays' microprocessor design, the TLB is widely used to speed up the translation speed from virtual address to physical address. Based on the adverse design, an applicable TLB structure supporting the different page sizes besides the address translation is proposed. In addition, a DVS technology is used reducing the leakage power in the TLB's memory cells by 90%.