The Physical Design of An Electronic System Certification Chip
Songlin Lai · China Integrated Circuit · 2010
In order to prevent illegally cloning of electronic products,the physical design of a system certification chip FD310S which protected the electronic system is introduced.Based on Hua Hong NEC 0.35 μm 1P3M technology,the timing closure design flow of Soc Encounter is used,including floorplan,timing-driven placement,static timing analysis and optimization,clock tree synthesis and timing-driven routing.After achieving timing closure,the connection between a special shape reused I/O pad and the power rings of whole chip are created in Virtuoso environment.The design has successfully passed the DRC (Design Rule Check) and LVS (Layout Versus Schematic).