Research of High-Speed Pipelined Floating-Point Multipfier Design
Xiaoyong Liu · Dianzi Ke-ji Daxue xuebao · 2007
A novel pipelined multiplier IP chip-core which supports single extended precision 43b floating point is designed.This design takes the advantage of modified Booth3 algorithm,and proposes a hybrid tree-shaped compression array.A new architecture of double multiplication channel six-stage pipeline is also proposed in this paper.Being implemented on FPGA,the operation performance of this in multiplier achieves 143.6 MFLO/S(Million Floating Point Operations Per Second)which is 47% higher than that of the similar multiplier unit recently provided by the Altera corporation.The experimental results show that this design can efficiently enhance the overall performance of multiplier.