Design of PCI-1149.1 Boundary-scan Master Controller
Cat Lab · JOURNAL OF ELECTRONIC MEASUREMENT AND INSTRUMENT · 2006
JTAG master unit is a very important circuit in the boundary-scan test environment. In this paper, we design a PCI-1149.1 Boundary-Scan Master Controller. We not only design a JTAG master core based on the finite state machine, but also employ First-In-First-Out (FIFO) technique in the master core to improve the test speed of boundary-scan. After simulated with MAX+PLUS II, the core is successfully integrated in a FPGA and used in a PCI-1149.1 controller now. Experiment results prove our JTAG master core and PCI-1149.1 Boundary-Scan Master Controller are correct.