Design of a VLSI architecture for a high performance QAM equalizer for HDTV receiver
Bo Wang · China Integrated Circuit · 2008
An all-digital QAM equalizer architecture is presented for HDTV receiver chip. This equalizer incorporates forward filter, error judge, coefficient updating and decision-feed back equalizer. This equalizer adopts CMA and DD-LMS algorithm. It emphasizes on realizing the VLSI(very large scale integrated-circuit). the rule between the algorithms, the selection of step and filter’ s coefficient. At the same time, the circuit attains trade-off among performance, area and power by applying simplicity in logic, recode technology and other optimization measure.