A high speed FIR filter design based on MATLAB and FPGA device
Yan Sun · Information technology newsletter · 2006
FIR filter is a basic processing unit for digital signal in common use.This paper presents a scheme which is designed with a FIR filter of high linear phase and can effectively realized in FPGA.This structure is made into effect by a rational division of the high-speed multiplier and recoganization in Wallace adder array tree with the aide of pipelining technology.The orders and the coefficients of the filter may flexibly be tuned,and it may suit to versatile applications.It is a better scheme for designing high speed digital filter through the programming and debugging.