Implement of 32 Orders FIR Filter on FPGA
Liang Benren · Modern Electronics Technique · 2009
Windows function design method of FIR digital filter is introduced,and the parallel distributed arithmetic is used to implement a 32 orders FIR digital filter.Using the Altera′s Stratix series FPGA to design a new structure of FIR.Using the ROM in FPGA,this design can convert convolution to summation.Thus,a high process speed is improved and the Logic Elements(LE) is saved.The result of simulation shows that the max speed of FIR filter can arrive at 200MHz based on parallel distributed arithmetic.