Low Power Interconnects Design for General Switch Box Based FPGA
Lingli Wang · Fudan xuebao. Ziran Kexue ban · 2012
In order to reduce the interconnect power dissipation,a fast architecture evaluation framework called FDPAef is proposed,and a proceed for optimizing the power delay product is established,for popular general interconnect architecture of FPGA.Different FPGA architectures based on the new general switch box(GSB) are evaluated and optimized with FDPAef framework,resulting in a low power architecture.The experimental MCNC benchmark result shows that compared to the common CS/BS interconnect architecture,9.9% power delay product decrease and 10.7% area decrease are achieved by this GSB interconnect architecture.