Efficient VLSI Design and Implementation of Decimation Filter for 2~(nd) ΣΔA/D Converter
Chungan Peng · Beijing Daxue Xuebao. Zirankexueban · 2007
The authors describes an efficient design and implementation of a decimation filter for high resolution 2~(nd) ΣΔ A/D converter.A new universal multiplier-free VLSI structure is proposed to implement 2-time decimation for half band filters and a high-order invsinc corrector filter,the whole filter is realized without any multiplier or RAM or ROM,and the 2~(nd) ΣΔ A/D converter reaches a 16-bit resolution with low cost.