The Synthesizability of Verilog HDL at the RTL Level Description
Fen Wei · Acta Scientiarum Naturalium Universitatis Neimongol · 2000
Synthesis is a procedure which transforms a high level of abstraction into a lower level description. At present, synthesis tools transform a structural description of RTL(Register Transfer Level) into Gate Level Netlist. The Verilog HDL language is structured and procedural, like the C programming language, Some statements and structures based on simulation and suited to syntax can′t be transformed into logic unit. So we should avoid those statements and structures which can′t be supported by synthesis tools.We present the basic approach to design program which can be synthesized at the RTL level description of Verilog HDL.