Design of a 32-bit Multi-Thread Packet Processing Micro-Engine
Shengbing Zhang · Journal of Chinese Computer Systems · 2006
Thread level parallel processing is one of the most important problems for high speed packet processing. This paper proposed a packet processing engine architecture called NRS05, that promotes the efficient dynamic thread scheduling for hiding long latency operations and coping with pipeline stalls. A dynamic thread scheduling scheme is presented by a mixed-grained multi-thread mechanism. Not only the performance of single packet processing is satisfied, but also the processor occupation probability for all threads are the same. And then data dependence and control dependence resolving methods and zero overhead context switching mechanism are also included. Finally this micro-engine is synthesized and verified, and the results suggest that the architecture of NRS05 is an attractive prospect for use in packet processing.