An FPGA implementation of single precision floating-point multiplier
Mao Xue · Application of Electronic Technique · 2010
An FPGA implementation of single precision floating-point multiplier is introduced in this thesis. With the usage of modified redundant Booth3 with bias and leapfrog Wallace tree, and the application of partial addition in fixed-point multiplication, the efficiency of the 5 -stage multiplier is promoted. Moreover, a module dealing with special values is introduced to perfect the function of the multiplier. The verification of the multiplier is accomplished on Altera DE2.