An Adaptive and Selective Instruction Active Push Technique for Multi-core Architecture
Jizhong Zhao · Journal of Chinese Computer Systems · 2013
Correct and effective instruction prefetching strategy is key technique to avoid instruction miss.Unfortunately,correctness and accuracy of instruction prefetching is not very precise,and the utilization ratio of memory bandwidth is relative low,which lead to instruction miss.This paper proposes an adaptive and selective instruction active push technique for multi-core architecture,called ASIAP.On one hand,in order to avoid the cache pollution and increase the prefetching validity,we perform instruction prefetching precisely as far as possible;on the other hand,part of non-sequential type prefetching are responded preferentially by a specific instruction active push unit adaptively and selectively,which decreases the possibility of fetching the useless instructions in the wrong path.We evaluate ASIAP with other prefetching strategies such as Next_Line、Target_Line、Wrong_Path、BTA、Markov and CFGP.Simulation result indicates that,under the configuration of 2 cores to 16 cores,relative to other strategies,ASIAP improves prefetching accuracy by average 3.7%-28.71%,and reduces of L1 I-Cache miss rate by average 3.3%-14.39%.