Design and implementation of a high speed floating-point multiply unit
Chao Ma · 2013
Floating-point multiplication unit has been widely used in Scientific Computing,Digital Signal Processing,Video Image Processing,and Graphic Processing.The single precision floatingpoint multiplier including 6level full pipeline was designed and implemented based on floating-point multiplication processing power needed by graphics processing unit.The modified booth algorithm was used in the partial product formation.The 4-2and 3-2mixed Wallace tree structure was employed in the partial product compression.By using Synopsys’s VCS to complete the function verification of the design under test and DC to synthesize the design under the 0.13um process library,the processing speed can reach 2.7Gflops,which met the requirements of the graphic processor.