Research and realization of a controller used for passive parallel asynchronous configuration of FPGA
Xia Yu-bao · Journal of Hefei University of Technology · 2008
In order to configure the FPGA quickly and conveniently,this paper presents a method—first downloading the program to Flash,and then downloading it to FPGA controlled by CPLD.Because no data in Flash will be lost if there is power failure,it solves the problem that the data will be lost if the power is off.A concrete hardware circuit and a programming thought for the software module are described.The simulation test proves that this design is feasible.