Implementation of variable block-size mostion estimation on FPGA
BI Du-yan · Computer Engineering and Applications Journal · 2007
The adoption of multiple macroblock partitions with variable block sizes is one of the main reasons behind the high efficiency of H.264 video coding standard.Unfortunately,repeating Sum of Absolute Difference(SAD) calculations for every possible block size introduces a heavy computational cost,in order to reduce the encdoer complexity,this paper proposes a hardware architecture for integrate Full Block Match Algorithm(FBMA),with reusing a common set of SAD computations for motion estimation of small blocks and a 2D shifting search window,the processing speed is greatly promoted.Simulation shows that it can get 41 MVs and the responeding SAD within only 324 circles,and the processing speed is nearly six times as fast as the other hardware solutions