Architecture design of superscalar embedded TURBO52 microprocessor
Wu Xiao · Application of Electronic Technique · 2009
In this paper, it is firstly give the background and the considerations to follow this technological roadmap of design the TURBO52. It then introduces the architecture design of instruction double issue super scalar pipeline, including the double-issue superscalar, branch prediction, dynamical execution and memory management. The various test patterns in running real applications indicates that ,under the same work clock frequency, the TURBO52 outperforms over 30 times faster than its traditional counterpart. However, owing to no implementation of data-cache and the three-layer-memory-hierarchy, the performance over 100 MHz is supposed to be hampered.