Area Efficient VLSI Design of BCH Decoder
Xianju Zeng · Microcomputer Information · 2010
VLSI design of an area-efficient BCH(8191,8087) decoder for ECC system of NAND Flash was present. With characteris- tics of NAND Flash ECC system taken into account, the circuit ,which was designed by using software and hardware co -design methodology and optimized 2 stage pipeline structure was implemented 。 Based on the four steps of ECC system, the improved Berlekamp-Massey iterative algorithm, and the FFM(finite field multiplier) series-parallel connection was used during the solving the key equation process, which effectively reduced the area of BCH decoder, making the suitable for ECC system of NAND flash.