A Low Power BIST Methodology Based on Two-mode LFSR
Longxing Shi · Journal of Electron Devices · 2004
A new low-power BIST structure with a creative two-mode LFSR is proposed. Traditional LFSR's power consumption is large because it produces large amounts of vectors. In order to reduce numbers of vector without influencing fault coverage, we propose a new BIST structure with two-mode LFSR. The paper first introduces the basic knowledge of power metric and delay model. Then the matrix computation applied in resolving two-mode LFSR is proposed. The methodology of how to resolving the matrix equation is given. The new BIST structure with two-mode LFSR and the Simulated Annealing Algorithm used in Grouping Detecting Vectors is present afterwards. Finally, the experiment based on benchmark circuits shows that this structure can reduce more than 70% of test power consumption without loss of fault coverage.