The Physical Design Solution for Million-Gate SoC Under VDSM
Hao Min · Fudan xuebao. Ziran Kexue ban · 2006
Facing lots of challenges in VDSM it takes much time or maybe fail to achieve design closure for physical design of today's SoC using traditional design flow.In order to accelerate the design closure,new design methodology must be explored.Here the detail problems under VDSM are analyzed,and new design solutions to enhance the backend design of VLSI by presenting an example of physical design of a 2 million gates wireless communication chip,together with key issues such as floorplan,power planning,crosstalk fixing are studied.