Design and Implementation of Inter/Deinterleaver
Yusheng Wang · Jisuanji gongcheng · 2011
To decrease the time delay of an inter/deinterleaver,a design scheme of a small-time-delay-packeted inter/deinterleaver is presented based on the Intersat Earth Station Standards(IESS).The time delay is analyzed and the scheme is implemented by FPGA.With typical inter/ deinterleaver data buffer modeling and imitated-original data stimulating,the simulation is completed.Based on hardware test bed,the logic-analyzed test is finished and part test results are given.It is proved that the scheme is valid and practical.