Design of a CMOS Error Amplifier Uesd in LDO
Zhan Ke · Microelectronics & Computer · 2007
Using 0.6μm standard process designed and realized A Error Amplifier,which can be used an internal Error Amplifier in LDO. This Error Amplifier can opeate under a wide range of power supply from 2.5V to 6.5V and insensitive to process variatin, especilly for temprature. Simulation results indicated: under the power supply of 2.5V～ 6.5V, the common input voltage is 0.7V～1.465V, the diference input voltage is ±2.5VT,open-loop voltage gain is about 75dB, phase margin is about 65°, unity gain bandwidth is about 9.4MHz, common mode rejection ratio is about 74dB, power supply rejection ratio is about 97.5dB, slew rate is about 18V/μs.